Traditional semiconductors and IC devices are typically packaged in a variety of ways to provide redistribution from the terminals on the die to a spacing that is conducive to cost effective printed circuit board (“PCB”) fabrication techniques. In many cases, the size and distance between die terminals is so small that the device cannot be connected to the final PCB without some sort of fan out or routing. The packages also serve to protect the fragile silicon or provide additional functions such as thermal management or near device decoupling. In many cases, the size and distance between die terminals is so small that the IC device cannot be connected to the final PCB without some sort of re-routing interface.
Most IC devices are produced with terminals in either a peripheral pattern that runs along the edges of the IC device or an area array pattern that spans across the surface of the IC device. A main method for attachment when the terminals are in an area array pattern is to connect the terminals with solder. Basically, the package has an array of terminals that correspond to the IC device terminals. Solder is applied the terminals on the IC device and/or the package and reflowed to create the mechanical and electrical connection in a process commonly called flip chip attachment. In a flip chip attachment the IC device is flipped over to mate the terminals on the die to the terminals on the IC package substrate.
The IC devices in these types of packages are often under filled with an epoxy of some type to provide support and strength to the solder joints. The epoxy protects the solder joints during use from thermal expansion, miss-match and/or shock. In both cases, the connection of the IC device to the package is generally not reworkable once packaged and if there is a missing or broken connection it is difficult to repair.
Once the IC devices are packaged, they are usually tested in a variety of ways to determine the reliability and performance of the IC devices in the package as they would be used in the final application. In many cases, the functional performance of the IC device is not known prior to placing it into the package and if the packaged IC device fails testing the cost of the package and processing is lost.
A packaging method that has increased in popularity in recent years is called Wafer Level Packaging, where the packaging materials are applied to the IC devices directly while they are still in the wafer format prior to dicing. This method has shown to be effective for relatively small pin count devices and has some advantages over handling individual IC devices and packaging them in an offline operation. Wafer Level packages tend to have routing and termination that is within the footprint of the die and not fanned out due to the fact that the fan out would be cut when the wafer is diced.
Area array packaging has been utilized for many years, and provides a method for interconnecting IC devices with larger terminal counts than peripheral lead packaging. In general, the area array packaging is more expensive due to the larger pin counts and more sophisticated substrates required. The main limitations for area array packaging are the terminal pitch, thermal management, cost, ability to rework faulty IC devices and reliability of the solder joints.